Rev2

This is the Torii platform definition for Squishy rev2 hardware. If you are for some reason using Squishy rev2 as a general-purpose FPGA development board with Torii, this is the platform you need to invoke.

Important

This platform is for specialized hardware, as such it can not be used with any other hardware than it was designed for. This includes any popular FPGA development or evaluation boards.

Note

There are no official releases of the Squishy rev2 hardware for purchase as it is currently in the early engineering-validation-test phases, and will likely change drastically before any are offered.

class squishy.gateware.platform.rev2.SquishyRev2

Squishy hardware, Revision 2.

This Torii platform is for the first revision of the Squishy SCSI hardware. It is based on the Lattice ECP5-5G Specifically the LFE5UM5G-45F and is built to be as flexible as possible, as such it is split between the main board, the SCSI PHY, and the various connectors boards.

The hardware design files can be found in the hardware repository on GitHub under the release/rev2-evt tree.

Warning

Squishy rev2 is currently in engineering-validation-test, and is unstable, the hardware may change and new, possibly fatal errata may be found at any time. Use with caution.

clk_domain_generator

alias of Rev2ClockDomainGenerator

pack_artifact(artifact: bytes) → bytes

Pack bitstream/gateware into device artifact.

Parameters:

artifact (bytes) – The input data of the result of gateware elaboration, typically the raw FPGA bitstream file.

Returns:

The resulting packed artifact for DFU upload.

Return type:

bytes

build_image(name: str, build_dir: Path, boot_name: str, products: BuildProducts) → Path

Build multi-boot compatible flash image to provision onto the device.

Parameters:

  • name (str) – The name of the flash image to produce.

  • build_dir (Path) – Output directory for the finalized flash image.

  • boot_name (str) – The name of the bootloader in the build products

  • products (BuildProducts) – The resulting build products from the bootloader build.

Returns:

The path to the resulting image file.

Return type:

Path

class squishy.gateware.platform.rev2.Rev2ClockDomainGenerator(*args, src_loc_at: int = 0, **kwargs)

Clock domain and PLL generator for Squishy rev2.

This module sets up 3 primary clock domains, sync, usb, and scsi. The first domain sync is the global core clock, the usb domain is a 60MHz domain originating from the ULPI PHY. The final domain scsi is the SCSI PHY domain.

Variables:

pll_locked (Signal) – An active high signal indicating if the PLL is locked and stable.