Rev1

This is the Torii platform definition for Squishy rev1 hardware. If you are for some reason using Squishy rev1 as a general-purpose FPGA development board with Torii, this is the platform you need to invoke.

Important

This platform is for specialized hardware, as such it can not be used with any other hardware than it was designed for. This includes any popular FPGA development or evaluation boards.

Note

There are no official releases of the Squishy rev1 hardware for purchase, and building one is not recommended due to the current hardware errata for the platform.

class squishy.gateware.platform.rev1.SquishyRev1

Squishy hardware, Revision 1.

This Torii platform is for the first revision of the Squishy SCSI hardware. It is based on the Lattice iCE40-HX8K and was primarily built to target SCSI-1 HVD only.

The hardware design files can be found in the hardware repository on GitHub under the release/rev1 tree.

clk_domain_generator

alias of Rev1ClockDomainGenerator

pack_artifact(artifact: bytes) → bytes

Pack bitstream/gateware into device artifact.

On Squishy rev1 platforms, there is no additional processing needed so this is effectively a no-op.

Parameters:

artifact (bytes) – The input data of the result of gateware elaboration, typically the raw FPGA bitstream file.

Returns:

The input bytes from artifact

Return type:

bytes

build_image(name: str, build_dir: Path, boot_name: str, products: BuildProducts) → Path

Build multi-boot compatible flash image to provision onto the device.

Parameters:

  • name (str) – The name of the flash image to produce.

  • build_dir (Path) – Output directory for the finalized flash image.

  • boot_name (str) – The name of the bootloader in the build products

  • products (BuildProducts) – The resulting build products from the bootloader build.

Returns:

The path to the resulting image file.

Return type:

Path

class squishy.gateware.platform.rev1.Rev1ClockDomainGenerator(*args, src_loc_at: int = 0, **kwargs)

Clock domain and PLL generator for Squishy rev1.

This module sets up two clock domains, usb and sync. The usb domain a 60MHz clock domain, and is fed from an external ULPI phy, where as the sync domain is the primary core clock domain and set for 100MHz and is fed from the global system input clock.

Variables:

pll_locked (Signal) – An active high signal indicating if the PLL is locked and stable.