Gateware Library#

The Squishy gateware library is broken into three main parts. The first is the squishy.gateware.core module, this contains all of the core infra for Squishy. Next is the squishy.gateware.platform module, this contains the torii platform definitions for various bits of Squishy hardware. Finally there is the squishy.gateware.scsi module, this is where all of the SCSI machinery is for use in torii HDL projects.

class squishy.gateware.SquishyPlatform(*args, **kwargs)#

Squishy Base Platform

This is a base platform for Squishy hardware designs. It is built to abstract away a chunk of the things that would be constantly repeated for new Squishy platforms and variants.

The primary things that are here are as follows:
  • usb_vid - The USB Vendor ID

  • usb_pid_app - The USB PID for the main gateware

  • usb_pid_boot - This USB PID for the bootloader

  • usb_mfr - The USB Manufacturer string

  • usb_prod - The USB PID to string mapping

  • scsi_vid - The default SCSI Vendor ID

The things that the platforms are expected to provide are as follows:
  • revision - The platform revision

  • clock_domain_generator - The Torii Elaboratable PLL/Clock Domain generator for this Squishy platform

  • pll_config - The PLL configuration for the clock_domain_generator

Platforms are also still required to inherit from the appropriate torii.vendor.platform in order to properly be used.

property usb_vid: int#

The USB Vendor ID used for Squishy endpoints

property usb_pid_app: int#

The USB PID for the main Squishy gateware

property usb_pid_boot: int#

The USB VID for the Squishy bootloader

property usb_mfr: str#

The USB Manufacturer string

property usb_prod: dict[int, str]#

The USB VID to USB Product string mapping

property scsi_vid: str#

The SCSI Vendor ID

abstract property revision: float#

The hardware platform revision

abstract property clock_domain_generator: Elaboratable#

The Torii Elaboratable that is the PLL/Clock Domain generator for this Squishy platform

abstract property pll_config: dict[str, int]#

The PLL configuration for the given clock_domain_generator