Peripherals

class squishy.gateware.peripherals.spi.SPIInterface(*, clk: ~torii.build.dsl.Subsignal, cipo: ~torii.build.dsl.Subsignal, copi: ~torii.build.dsl.Subsignal, cs_peripheral: ~torii.build.dsl.Subsignal, cs_controller: ~torii.build.dsl.Subsignal, mode: ~squishy.gateware.peripherals.spi.SPIInterfaceMode = <SPIInterfaceMode.BOTH: 3>, cpol: ~squishy.gateware.peripherals.spi.SPICPOL = SPICPOL.HIGH, cpha: ~squishy.gateware.peripherals.spi.SPICPHA = SPICPHA.RISING, reg_map: ~torii.lib.soc.csr.bus.Multiplexer | None = None) → None

An SPI interface that can act as both an SPI controller and/or an SPI peripheral.

Parameters:

  • clk (Subsignal, inout) – The SPI bus clock line.

  • cipo (Subsignal, inout) – The SPI bus CIPO line.

  • copi (Subsignal, inout) – The SPI bus COPI line.

  • cs_peripheral (Subsignal, in) – The chip-select signal to route to the SPIPeripheral

  • cs_controller (Subsignal, out) – The chip-select signal to route out from the SPIController

  • mode (SPIInterfaceMode) – The mode this SPI interface represents, either a SPI Controller, a SPI Peripheral, or both. (default: <SPIInterfaceMode.BOTH: 3>)

  • cpol (SPICPOL) – The SPI bus clock electrical idle. (default: HIGH) (default: <SPICPOL.HIGH: 1>)

  • cpha (SPICPHA) – The SPI bus clock phase. (default: RISING) (default: <SPICPHA.RISING: 0>)

  • reg_map (torii.lib.soc.csr.Multiplexer | None) – The CSR register map to feed the SPIPeripheral if mode is either PERIPHERAL or BOTH (default: None)

Attributes:

active_mode (Signal) – This signal is only present if mode is BOTH. It controls the output-enables for the COPI, CIPO, and CLK lines depending if it is high, for the controller, or low, for the peripheral.

controllerSPIController

The SPIController module if mode is CONTROLLER or BOTH.

peripheralSPIPeripheral

The SPIPeripheral module if mode is PERIPHERAL or BOTH.

class squishy.gateware.peripherals.spi.SPIInterfaceMode(value)

The operating mode for SPIInterface

CONTROLLER = 1

Enable the SPIController inside SPIInterface

PERIPHERAL = 2

Enable the SPIPeripheral inside SPIInterface

BOTH = 3

Enable both the SPIController and the SPIPeripheral inside SPIInterface

class squishy.gateware.peripherals.spi.SPIController(*, clk: Signal, cipo: Signal, copi: Signal, cs: Signal, cpol: SPICPOL = SPICPOL.HIGH, cpha: SPICPHA = SPICPHA.RISING) → None

A generic SPI Bus Controller for a SPI bus with one peripheral on it. (for now)

Parameters:

  • clk (Signal, out) – The clock generated for the SPI bus from this controller.

  • cipo (Signal, in) – The data signal coming in from the peripherals on the bus.

  • copi (Signal, out) – The data signal going out to the SPI bus from this controller.

  • cs (Signal, out) – The selection signal for the device on the SPI bus.

  • cpol (SPICPOL) – The SPI bus clock electrical idle. (default: HIGH) (default: <SPICPOL.HIGH: 1>)

  • cpha (SPICPHA) – The SPI bus clock phase. (default: RISING) (default: <SPICPHA.RISING: 0>)

Attributes:

  • cs (Signal) – SPI Chip Select.

  • xfr (Signal) – Transfer strobe.

  • done (Signal) – Transfer complete signal.

  • wdat (Signal(8)) – Write data register.

  • rdat (Signal(8)) – Read data register.

class squishy.gateware.peripherals.spi.SPIPeripheral(*, clk: Signal, cipo: Signal, copi: Signal, cs: Signal, reg_map: Multiplexer | None = None) → None

A SPI peripheral that exposes a set of registers to the SPI bus.

Parameters:

  • clk (Signal, in) – The incoming SPI Bus clock signal

  • cipo (Signal, out) – The output from the SPI peripheral to the bus.

  • copi (Signal, in) – The input from the controller on the SPI bus to the peripheral.

  • cs (Signal, in) – The chip-select signal from the SPI bus to indicate this peripheral should be active.

  • reg_map (torii.lib.soc.csr.Multiplexer) – The CSR register map to expose to the SPI bus. (default: None)

class squishy.gateware.peripherals.spi.SPICPOL(value)

The state of the electrical idle for the SPI controller clock

LOW = 0

SPI Controller clock is electrical idle high

HIGH = 1

SPI Controller clock is electrical idle low

class squishy.gateware.peripherals.spi.SPICPHA(value)

The phase of the SPI controller clock

RISING = 0

Data is sampled on the rising edge

FALLING = 1

Data is sampled on the falling edge

class squishy.gateware.peripherals.flash.SPIFlashOp(value)

The current SPI Flash Operation being completed

NONE = 1

No Operation

ERASE = 2

Sector Erase

WRITE = 3

Page Write

READ = 4

Page Read

class squishy.gateware.peripherals.psram.PSRAMOp(value)
class squishy.gateware.peripherals.psram.SPIPSRAMCmd(value)

SPI PSRAM Command Opcodes

class squishy.gateware.peripherals.psram.SPIPSRAM(*, controller: SPIController, write_fifo: AsyncFIFO | None = None, read_fifo: AsyncFIFO | None = None) → None

This module primarily implements the SPI interface for the ISSI IS66WVS2M8ALL/BLL/IS67WVS2M8ALL/BLL SPI PSRAM. The datasheet can be found here.

Parameters:

  • controller (SPIController) – The SPI Controller to use, typically from an SPIInterface module instance.

  • write_fifo (torii.lib.fifo.AsyncFIFO | None) – The data storage FIFO for transfers to the PSRAM. (default: None)

  • read_fifo (torii.lib.fifo.AsyncFIFO | None) – The data storage FIFO for transfers from the PSRAM. (default: None)

Attributes:

  • ready (Signal, out) – The PSRAM FSM is in the IDLE state and ready to start a transaction with start_r or start_w

  • start_addr (Signal[24], in) – The address to start the transaction at.

  • curr_addr (Signal[24], out) – The current address of the next access of the state machine. Due to how the PSRAM wraps ever 1024 bytes, this is auto-incremented and wrapped appropriately.

  • rst_addrs (Signal, in) – Reset curr_addr to the address given in start_addr

  • byte_count (Signal[24], in) – The number of bytes to be transferred in the given read or write request

  • start_r (Signal, in) – Starts a read transaction of byte_count bytes from the device into the read_fifo, starting from curr_addr, setting up the address as needed for the device.

  • start_w (Signal, in) – Starts a write transaction of byte_count bytes from the write_fifo, starting from curr_addr, setting up the address as needed for the device.

  • done (Signal, out) – The Transaction was fully completed and the FSM is about to transition into the IDLE state waiting for another transaction to start.

  • finish (Signal, in) – Signal to the FSM that our transaction is completed so it can wrap up.