squishy.gateware.core.pll

class squishy.gateware.core.pll.ICE40ClockDomainGenerator(*args, src_loc_at=0, **kwargs)

PLL Wrapper for iCE40 based Squishy platforms.

This elaboratable declares two clock domains, usb and sync. The usb domain is a 60MHz clock coming from a ULPI phy, and the sync domain is a PLL’d up value from the system clock.

In Squishy rev1 the PLL for the sync domain is set for 100MHz.

class squishy.gateware.core.pll.ECP5ClockDomainGenerator(*args, src_loc_at=0, **kwargs)

PLL Wrapper for iCE40 based Squishy platforms.

This elaboratable declares two clock domains, usb and sync. The usb domain is a 60MHz clock coming from a ULPI phy, and the sync domain is a PLL’d up value from the system clock.

In Squishy rev2 the PLL for the sync domain is set for 300MHz.

Variables

pll_locked (Signal) – An active high signal indicating if the ECP5 PLL is locked and stable.